The present disclosure relates generally to interconnection packaging for integrated circuits and, more particularly, to a structure and method for wiring translation between grids having non-integral pitch ratios in chip carrier modules.
Integrated circuit chips may be packaged in a variety of ways, depending upon the performance and reliability requirements of the system in which they are used. High end integration schemes, sometimes referred to as multichip modules (MCMs) or single chip modules (SCMs), normally include at least one integrated circuit chip which is mounted to an insulating substrate. The insulating substrate, which may be ceramic, for example, has one or more wiring layers therein and thus provides a medium for electrical connections between chips (on an MCM) and/or between modules (for an MCM or a SCM). The wiring layers of the substrate are terminated at each of the top and bottom surfaces of the substrate in an array of I/O pads for interfacing to the chip and to a circuit board or other higher level module. The I/O pads may be a part of a controlled collapse chip contact (C4), ball grid array (BGA) or other connection scheme.
In a conventional MCM design, a logic service terminal (LST) grid (or via grid) located in the substrate provides an interface between the redistributed power, ground and signal terminals from a chip, and an X-Y wiring area. The X-Y wiring area comprises X and Y wiring planes which establish connections from one chip to another chip, or from one chip to pins on the MCM substrate. Typically, the LST grid has a pitch which is an integral multiple of the pitch of the chip I/O grid (e.g., C4 grid) for ease of interconnection therebetween. However, such a dependent relationship may be disadvantageous in that neither the LST grid nor the C4 grid may be changed or redesigned independently of one another.
In the event of a design change in the LST grid (e.g., for device miniaturization purposes), there is a resulting corresponding change to the C4 grid in order to maintain an integral multiple pitch ratio therebetween. As a result of a change in the C4 grid, there is also a change in chip design, wafer probes, temporary chip attachments (TCAs), and the like. Conversely, a design change in a C4 grid results a corresponding change in the LST grid. As a result, a design change in the LST grid begs certain technological advances in process fabrication areas such as ceramics, punch diameter, line width, masks, green sheet (GS) thickness, pastes, and the like. Thus, it can be seen that a design change in one grid aspect of an MCM may lead to costly changes in other aspects of the MCM.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.
In a preferred embodiment, the first translation layer further includes a first plurality of signal interconnects, the first plurality of signal interconnects each having a jog line elongated along the x-axis direction. The second translation layer further includes a second plurality of signal interconnects, the second plurality of signal interconnects each having a jog line elongated along the y-axis direction. Each of the jog lines in the first plurality of signal interconnects is disposed between an upper via contact and a lower via contact in the first translation layer. Similarly, each of the jog lines in the second plurality of signal interconnects is disposed between an upper via contact and a lower via contact in the second translation layer. Each individual upper via contact in the first translation layer is in electrical communication with a corresponding point in the first grid, while each individual lower via contact in the first translation layer is in electrical communication with a corresponding upper via contact in the second translation layer. Furthermore, each individual lower via contact in the second translation layer is in electrical communication with a corresponding point in the second grid. Preferably, the first grid is a C4 grid and the second grid is a logic service terminal (LST) grid.